An 8051-compatible core, which also has a 16-bit DSP-like extension mapped to the opcode 0xA5 (reserved in plain 8051)
Might be in some connection with the Appotech’s 8051-compatible core.
The OpenRISC 1000 (or1k), all in its glory.
It might be the first 32-bit CPU core that JieLi has ever used (and deployed).
This architecture can be seen used e.g. in the AC4100 (CD003) chip.
Analog Devices’ Blackfin, all in its glory.
The vendor’s toolchain package provides two separate compilers: dv10 and dv12. So either there are some custom additions and changes to this architecture, or idk.
At least, they both produce an ELF file which tells that this is the “Analog Devices Blackfin” machine, and the flags are zero in both cases.
The JieLi’s custom architecture to be Independent and Free /as in freedom/!!
Seemingly this is heavily based off (or inspired by) the Analog Devices’ Blackfin. This can be seen in the instruction encoding scheme (although I’ve thought that this was like the ARM Thumb.. but no!), the algebraic notation in the assembly language, etc!
Second generation of the pi32 architecture.
A cut-down variant of pi32v2 (or rather, based on its architecturical decisions).
At least it’s used on the BD19 (AC632N) and BD29 (AC630N) series.